1. Field of the Invention
The present invention relates to a solid-state imaging device, a manufacturing method of the same, and an electronic apparatus such as a camera including the solid-state imaging device.
2. Description of the Related Art
As a solid-state imaging device, there is known an amplification type solid-state imaging device of which a representative example is an MOS image sensor such as a CMOS (Complementary Metal Oxide Semiconductor) image sensor. In addition, there is known a charge transfer type solid-state imaging device of which a representative example is a CCD (Charge Coupled Device) image sensor. These solid-state imaging devices are widely used in a digital still camera, a digital video camera, or the like. In recent years, as the solid-state imaging device mounted on a camera-attached cellular phone or PDA (Personal Digital Assistant), an MOS image sensor is widely used in terms of low power voltage, low power consumption, or the like.
In the MOS type solid-state imaging device, a unit pixel includes a photodiode serving as a photoelectric conversion unit and plural pixel transistors. The solid-state imaging device includes a pixel section (imaging area), where the plural unit pixels are arranged in a two-dimensional array shape, and a peripheral circuit area. The plural pixel transistors are formed as an MOS transistor and may include three transistors, that is, a transmission transistor, a reset transistor, an amplification transistor or four transistors in addition to a selection transistor.
FIG. 14 is a diagram illustrating the main elements of a charge reading unit of a pixel 102 in a general MOS solid-state imaging device 101 according to the related art. In the pixel 102, a p-type semiconductor well area 104 is formed on an n-type semiconductor substrate 103, for example. The p-type semiconductor well area 104 is provided with a photodiode 105 serving as a photoelectric conversion unit and a floating diffusion 108 formed as an n-type semiconductor area reading signal charges of the photodiode 5. A transmission transistor Tr1 is formed which includes a transmission gate electrode 111 formed with a gate insulating film 109 interposed between the photodiode 105 and the floating diffusion 108. A charge reading portion is formed in the transmission transistor.
The photodiode 105 is formed as a buried-type photodiode including an n-type semiconductor area 106 serving as a charge storage area which stores the signal charges and a p-type semiconductor area 107 also serving as a hole accumulation layer formed in the interface of the surface of the n-type semiconductor area 106. The p-type semiconductor area 107 is referred to as a hole charge storage area. The hole charge storage area 107 functions as inhibiting a dark current and is formed in a relatively high concentration p+ area. The n-type semiconductor area 106 serving as a charge storage area is also formed in a relatively high concentration n+ area. A relatively low concentration n-type semiconductor area (n−− area) with a necessary depth is formed continuously below the n-type semiconductor area 106. A depth D1 refers to a distance between the substrate surface and the bottom of an n-type semiconductor area 110. The n−− area 100 and the n+ area 106 form an n-type area of the photodiode 5. A side wall 112 formed of a two-layered insulating film is formed on a side of the transmission gate electrode 111 of the transmission transistor Tr1.
In the photodiode 105, the n-type semiconductor area 106 serving as the charge storage area is formed so as to partially overlap with the transmission gate electrode 111, and the hole charge storage area 107 is formed in an offset state so as to be slightly distant from the transmission gate electrode 111. This is because a reading characteristic of the signal charges stored in the n-type semiconductor area 106 is made satisfactorily. For example, when the hole charge storage area 107 is formed close to the transmission gate electrode 111, it is difficult to modulate the potential of a portion close to the transmission gate of the n-type semiconductor area 107 upon reading the charges, and thus it is difficult to read the signal charges. This is because the potential of the hole charge storage area 107 is fixed to a reference potential. That is, when the hole charge storage area 107 is close to the gate electrode 111, a gate voltage (reading voltage) Vtg of the transmission transistor Tr1 is increased, and thus it is difficult to read the signal charges. By separating the hole charge storage area 107 from the gate electrode 111, the potential of the portion close to the transmission gate of the n-type semiconductor area 106 is modulated, thereby reading the signal charges of the photodiode 105 easily.
Japanese Unexamined Patent Application Publication No. 2008-21925 and PCT application No. WO2003/096421 disclose a solid-state imaging device in which a hold charge storage area in a photodiode is formed in the offset state so as to be separate from a gate electrode.
Japanese Unexamined Patent Application Publication No. 11-274457 discloses a solid-state imaging device in which an n-type semiconductor area serving as a charge storage area extends to a gate portion more than a p-type semiconductor area also serving as a hole charge storage area.